The technical field of this invention is control of data transfers between data registers of a data processor and its associated data memory.
The concept of a single computer instruction causing a multiple memory accesses dates back at least to the IBM 370 series main frames, where they are called the load multiple or store multiple instructions (LM and STM). They are used to do fast bulk saves and restores of the contents of the register file. These instructions operate on a specified range of registers and attempt to operate as fast as possible. In the IBM 370 these instructions only stall if the data cache is busy. The number of registers operated on per cycle varies depending on the machine model, up to 4 registers per cycle for some latter models. The IBM 370 computer architecture does not support predication of these instructions.
Reduced instruction set computers (RISC), such as the PA-RISC architecture, typically support predicated operations. These RISC data processors replace the multicycle LM/STM type of instructions with groups of multiregister load and store instructions.
In VLIW systems, such as the TMS320C62x/C67x family of processors of Texas Instruments, adding some additional basic functionality to a D (load/Store) unit is almost free. In this case the D unit can provide additional computational power for inner loops when it is not doing loads or stores. The problem is that in some case you would like to use more of the D units time for non-storage work but still maintain control of the data flow from memory into and out of the register file.
This invention is a data processor operating in instruction cycles including an instruction permitting delayed memory accesses. A multiple cycle memory access unit issues a memory access delaying a predetermined number of instruction cycles between its activation and its initial data transfer. These memory accesses could be loads (data transfer from data memory to a central processing unit data register) or stores (data transfer from a data register to memory). In the preferred embodiment the multiple cycle memory access unit controls a predetermined plural number of such accesses. These accesses preferably are performed independently and in parallel with the instruction flow of the data processor, once the multiple cycle memory access unit has been activated.
The multiple cycle memory access unit delays a predetermined number of instruction cycles between sequential data transfers of the predetermined number of data transfers. This predetermined period may be the same as the initial delay or it may be determined independent of the initial delay.
The operation of the multiple cycle memory access unit is subject to predication on an instruction specified data registers. The operation subject to predication aborts upon detection of a predetermined state in the instruction specified data register. The operation subject to predication could be the data memory accesses or the actual data writes, or both. The multiple cycle memory access unit may abort the predicated operation on predication failure and continue with the next operation or abort the predicated operation and stop operation.
The multiple cycle memory access unit preferably provides predetermined register number cycling among the plural data registers. This cycling could be between an instruction specified data register and the next data register. Double word operations could be between two register pairs. The register cycling could begin with an instruction specified data register and cycle to a next higher data register number either with or without wrapping at the highest register number. The register cycling could begin with an instruction specified data register and cycle to a next lower data register number either with or without wrapping at the lowest register number.
The multiple cycle memory access unit preferably aborts operation and stops on a predetermined event, such as an external interrupt, an internal interrupt, a forward branch taken or a subroutine call. On such an aborted operation, the internal state of the multiple cycle memory access unit is saved into instruction visible and alterable memory. This instruction visible memory preferably includes control registers.
The multiple cycle memory access unit can be enabled and disabled by via instructions or bits in a control register. The multiple cycle memory access unit is loaded and activated by at least one special instruction or by a normal instruction in a special mode.